Imaging arrays comprised of multiple sensor pixels 100 are well known in the imaging art. Sensor pixels 100 typically include a switching element 210 such as a thin-film transistor (TFT), and a photoelectric conversion element 220 such as a photodiode. FIG. 1 shows a schematic equivalent pixel circuit for sensor pixels 100. The photoelectric conversion element 220 or photosensor is sensitive to incident radiation and can generate a number of charge carriers where the number depends on the radiation dosage. In imaging arrays composed of a plurality of pixels, the photogenerated carriers are usually temporarily stored across the internal capacitance of the sensor prior to readout. An additional on-pixel storage capacitor 230 can be added to each pixel to increase the pixel's charge capacity, Qpix. A task of the switching element 210 is to maintain the signal within the pixel and subsequently enable the readout of the signal. A signal of interest is typically represented by the change in charge carriers held at the floating node 240 of the pixel, which is typically manifested as a potential change of floating node 240. Aside from the device elements 210, 220, 230, the signal lines are also crucial to the functionality of the sensor pixel and the imaging array. The switching element 210 is controlled by the scan line 250 that dictates the time and duration of the signal charge release process. The data line 260 provides a path for the released charge carriers to the readout electronics. The bias line 270 provides the appropriate bias voltages for the photoelectric conversion elements 220.
A plurality of sensor pixels can be tiled in a matrix fashion to form an imaging array. FIG. 2 shows a schematic equivalent diagram of a 3×3 pixels imaging array that can be used for general radiation detection devices. The bias line 270 is shared among pixels in each column and is connected to the sensor bias circuitry. The ground line 340 is shared among pixels in each row parallel to the scan line 250. Lower electrodes 330 (not labeled in FIG. 2) of the on-pixel storage capacitors 230 are connected to the ground lines 340 that provide a common ground reference potential. The data line 260 is shared among pixels in each column and is connected to the readout electronics. The scan line 250 is shared among pixels in each row and is connected to the driving electronics. The driving circuitry provides the appropriate signals on scan lines 250 to release the signals stored on the floating nodes 240 of pixels 100 to the data lines 260 usually one row at a time, usually in sequence.
The incorporation of on-pixel storage capacitor 230 addresses several issues for the related art pixels where most of the signal charge is stored across the internal capacitance of the photoelectric conversion element 220. For one, the addition of an on-pixel storage capacitor 230 helps in boosting the pixel charge capacity Qpix. The charge capacity of the pixel dictates the maximum amount of photogenerated signal charge that can be stored in the pixel prior to readout. Qpix can be approximated by Qpix=Cpix×Vmax, where Cpix is sum of the internal capacitance of the photoelectric conversion element 220 (hereinafter denoted as Cpd) and the capacitance of the on-pixel storage capacitor 230 (hereinafter denoted as Cst), and Vmax is the maximum potential change allowed under normal operation of the pixel. For related art pixels where the on-pixel storage capacitor 230 does not exist, the magnitude of Cpix is dominated by Cpd. When Vmax is kept constant, the addition of the on-pixel storage capacitor 230 boosts the magnitude of Cpix so that Qpix increases. Boosting the pixel charge capacity may resolve clipping issues in imaging regions subjected to high exposures.
U.S. Pat. No. 7,524,711 discloses one method of fabricating on-pixel storage capacitors 230 for a TFT array backplane used in indirect X-ray sensors. FIGS. 3A-6A illustrates the top-down view of a pixel at various fabrication stages of the TFT array backplane 300. FIGS. 3B-6B illustrates the cross-sectional views of the pixel that corresponds to FIGS. 3A-6A. The cutting-plane line A-A′ for the cross-sectional views is shown in top-down view illustrations. Note that the sensor pixel TFT backplane structure 300 shown in FIG. 6A and FIG. 6B does not constitute the entire sensor pixel 100 illustrated in FIG. 1; it merely shows the fabrication steps for a switching element 210 and an on-pixel storage capacitor 230 as disclosed by U.S. Pat. No. 7,524,711.
The manufacturing method of the pixel TFT backplane 300 starts with the deposition of the first metal layer over a substrate 310. The first metal layer is then patterned using photolithography method to produce a gate line 250, a gate electrode 320 for the TFT 210, a lower electrode 330 of the on-pixel storage capacitor 230, and a ground line 340 connecting the lower electrode 330 in each sensor pixel 100. FIG. 3A and FIG. 3B respectively illustrates the top-view and cross-sectional view of the pixel TFT backplane 300 after the first photolithography step. Next, a first insulation layer 410 is deposited on the substrate, the gate line 250, the gate electrode 320, the lower electrode 330, and the ground line 340. A semiconductor layer 420 and a doped layer 430 (not shown in FIG. 4A for clarity) are sequentially formed to cover the substrate 310 and on the insulation layer 410. Next, photolithography is performed to pattern the semiconductor layer and the doped layer to define an island region above the gate electrode 320. FIG. 4A and FIG. 4B illustrates the top-view and cross-sectional view of the resulting structure, respectively. Follows, the second metal layer is deposited to cover the substrate including the island region and the insulation layer 410; photolithography is performed to pattern the second metal layer to form a data line 260, an upper electrode 510, a second electrode 520 connected with the upper electrode 510, a third electrode 530 connected with the data line 260. Accordingly, a gap is also formed removing part of the island region. FIG. 5A and FIG. 5B illustrates the top-view and cross-sectional view of the resulting structure, respectively. The upper electrode 510, lower electrode 330, and portion of the insulator layer 410 in between the two electrodes constitute the on-pixel storage capacitor 230. The gate electrode 320, the second electrode 520, the third electrode 530, the island, and the portion of the insulator layer 410 in between the island and the gate electrode 320 constitutes the TFT switching element 210. Subsequently, a passivation layer 620 is deposited cover the substrate including the second metal layer and the island gap opening. To enable connection between the on-pixel storage capacitor 230 and the photoelectric conversion element 220, a region of the passivation layer 620 is removed using another photolithography step. This aperture region 610 exposes a portion of the upper electrode 510. FIG. 6A and FIG. 6B illustrates the top-view and cross-sectional view of the resulting structure, respectively.
The on-pixel storage capacitor 230 implementation described above as well as those disclosed by U.S. Pat. No. 5,319,206 and U.S. Pat. No. 6,806,472 requires the electrode not connecting to the photoelectric conversion element 220 be biased independently from the photoelectric conversion element 220. The voltage applied to these terminals for each pixel is usually the ground reference potential or common potential as indicated by the pixel schematic diagram shown in FIG. 1. Consequently, the implementation requires additional routing lines to connect the lower electrode 330 in each pixel, such as ground line 340 shown FIGS. 3A-6A. It is generally desirable to reduce the number of routing lines in each pixel since larger routing line count may potentially reduce the manufacturing yield of the image sensor. The on-pixel storage capacitor 230 implementation described previously also places a constraint on the maxim area allowed by the storage capacitor. Referring to FIG. 6A the upper electrode 510 of the on-pixel storage capacitor 230 is deposited simultaneously as the data line 260 and the third electrode 530 of the TFT. Therefore, the upper electrode cannot span beyond those regions occupied by other electrodes, which would otherwise lead to shorting between electrodes. Consequently, the maximum area of the upper electrode 510 in each pixel is restricted to those areas not occupied by the data line 260 and the TFT. Similar statement can be said for the lower electrode of the on-pixel storage capacitor 230 and the scan line 250. Given that the thickness and build material of the insulator layer 410 is unchanged, Cst scales proportionally with the electrode area. Therefore, Cst is maximized when the area of both upper electrode 510 and lower electrode 330 are made as large as possible within the pixel. Please note that the area of the upper electrode 510 or lower electrode 330 must be smaller than p2, where p is the pixel pitch. This also places an upper limit on the maximum Qpix without having to modify other pixel metrics such as Cpd.